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ICS9EPRS525 idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 56-pin ck505 for embedded intel systems 1 datasheet pin configuration recommended application: 56-pin ck505 compatible clock, w/fully integrated vreg and series resistors on differential outputs for embedded applications output features: ? 2 - cpu differential low power push-pull pairs 7 - src differential push-pull pairs 1 - cpu/src selectable differential low power push-pull pair 1 - src/dot selectable differential low power push-pull pair 1 - src/se selectable differential push-pull pair/single-ended outputs 5 - pci, 33mhz 1 - usb, 48mhz 1 - ref, 14.318mhz key specifications: cpu outputs cycle-cycle jitter < 85ps src output cycle-cycle jitter < 125ps pci outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on all outputs src outputs meet pcie gen2 when sourced from pll3 features/benefits: supports spread spectrum modulation, 0 to -0.5% down spread supports cpu clks up to 400mhz uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning table 1: cpu frequency select table fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz usb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 111 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. reserved 100.00 33.33 14.318 48.00 96.00 pci0/cr#_a 1 56 sclk vddpci 2 55 sdata pci1/cr#_b 3 54 ref0/fslc/test_sel pci2/tme 4 53 vddref pci3/cfg0 5 52 x1 pci4/src5_en 6 51 x2 pci_f5/itp_en 7 50 gndref gndpci 8 49 fslb/test_mode vdd48 9 48 ck_pwrgd/pd# usb_48mhz/fsla 10 47 v ddcpu gnd4811 46cput0_lrs vdd96io 12 45 cpuc0_lrs dott_96_lrs/srct0_lrs 13 44 gndcpu dotc_96_lrs/s rcc0_lrs 14 43 cput1_f_lrs gnd 15 42 cpuc1_f_lrs vdd 16 41 vddcpuio srct1_lrs/se1 17 40 nc srcc1_lrs/se2 18 39 cput2_itp_lrs/srct8_lrs gnd 19 38 cpuc2_itp_lrs/srcc8_lrs vddpll3io 20 37 vddsrcio srct2_lrs/satat_lrs 21 36 srct7_lrs/cr#_f srcc2_lrs/satac_lrs 22 35 srcc7_lrs/cr#_e gndsrc 23 34 gndsrc srct3_lrs/cr#_c 24 33 srct6_lrs srcc3_lrs/cr#_d 25 32 s rcc6_lrs vddsrcio 26 31 vddsrc srct4_lrs 27 30 pci_stop#/srct5_lrs srcc4_lrs 28 29 cpu_stop#/s rcc5_lrs 56-tssop 9eprs525
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 2 56-pin ck505 for embedded systems pin description pin # pin name type description 1 pci0/cr#_a i/o 3.3v pci clock output or clock request control a for either src0 or src2 pair the power-up default is pci0 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via s mbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 0 of smbus address space . af ter the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cra#_en bi t located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cra# enabled. byte 5, bit 6 controls whether cra# controls src0 or src2 pair byte 5, bit 6 0 = cra# controls src0 pair (default), 1= cra# controls src2 pair 2 vddpci pwr power supply for pci clocks, nominal 3.3v 3 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for either src1 or src4 pair the power-up default is pci1 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via s mbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 1 of smbus address space . af ter the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the crb#_en bi t located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= crb# enabled. byte 5, bit 6 controls whether crb# controls src1 or src4 pair byte 5, bit 4 0 = crb# controls src1 pair (default) 1= crb# controls src4 pair 4pci2/tme i/o 3.3v pci clock output / trusted mode enable(tme) latched input. this pin is sampled on power-up as follows 0=overclocking of cpu and src allowed 1=overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 5 pci3/cfg0 i/o 3.3v pci clock output/configuration strap. see pci3 configuration table for more information 6 pci4/src5_en i/o 3.3v pci clock output / src5 pair or pci_stop#/cpu_stop# enable strap. on powerup, the logic value on this pin determines if t he src5 pair is enabled or if cpu_stop#/pci_stop# is enabled (pins 29 and 30). the latched value controls the pin function on pins 29 and 30 as follows 0 = pci_stop#/cpu_stop# 1 = src5/src5# 7 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable strap. this output is not affected by the state of the pci_stop# pin. on powe rup, the state of this pin determines whether pins 38 and 39 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 8 gndpci pwr ground pin for the pci outputs 9 vdd48 pwr power pin for the 48mhz output and pll.3.3v 10 usb_48mhz/fsla i/o 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. / fixe d 48mhz usb clock out p ut. 3.3v. 11 gnd48 pwr ground pin for the 48mhz outputs 12 vdd96io pwr power supply for dot96 outputs, 1.05v to 3.3v. 13 dott_96_lrs/srct0_lrs out true clock of low power differential src or dot96 with integrated 33 ohm rs. the power-up default function is src0. after power up, this pin function may be changed to dot96 via smbus byte 1, bit 7 as follows: 0= src0 1=dot96 14 dotc_96_lrs/srcc0_lrs out complement clock of low power differential src or dot96 with integrated 33 ohm rs. the power-up default function is src0#. afte r powerup, this pin function may be changed to dot96# via smbus byte 1, bit 7 as follows 0= src0# 1=dot96# 15 gnd pwr ground pin. 16 vdd pwr power supply, nominal 3.3v 17 srct1_lrs/se1 out true clock of low power differential src1 clock pair with integrated 33 ohm rs. / 3.3v single-ended output. the powerup default is 100 mhz src, - 0.5% downs p read. the p in function ma y be chan g ed via smbus b1b [ 4:1 ] 18 srcc1_lrs/se2 out complement clock of low powerl differential src1 clock pair with integrated 33 ohm rs / 3.3v single-ended output. the powerup d efault is 100 mhz src , -0.5% downs p read. the p in function ma y be chan g ed via smbus b1b [ 4:1 ] 19 gnd pwr ground pin. 20 vddpll3io pwr power supply for pll3 outputs. 1.05v to 3.3v. 21 srct2_lrs/satat_lrs out true clock of low power differentiall src/sata clock pair with integrated rs. 22 srcc2_lrs/satac_lrs out complement clock of low power differential push-pull src/sata clock pair with integrated 33 ohm rs. 23 gndsrc pwr ground pin for the src outputs 24 srct3_lrs/cr#_c i/o true clock of low power differential src clock pair with integrated 33 ohm rs./ clock request control c for either src0 or src 2 pair. the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. befo re configuring this pin as a clock request pin, the src output must first be disabled in byte 4, bit 7 of smbus address space . after the src outpu t is disabled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the crc#_en bit located in byte 5 of smbu s address space. byte 5, bit 3 0 = srcclk3 enabled (default) 1= crc# enabled. byte 5, bit 2 controls whether crc# controls src0 or src2 pair byte 5, bit 2 0 = crc# controls src0 pair (default), 1= crc# controls src2 pair
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 3 56-pin ck505 for embedded systems pin description (continued) pin # pin name type description 25 srcc3_lrs/cr#_d i/o complementary clock of low power differential src clock pair with integrated 33 ohm rs/ clock request control d for either src 1 or src4 pair. the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 vi a smbus. before configuring this pin as a clock request pin, the src output must first be disabled in byte 4, bit 7 of smbus address space . af ter the src output is disabled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the crd#_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= crd# enabled. byte 5, bit 0 controls whether crd# controls src1 or src4 pair byte 5, bit 0 0 = crd# controls src1 pair (default), 1= crd# controls src4 p air 26 vddsrcio pwr power supply for src outputs. 1.05v to 3.3v. 27 srct4_lrs out true clock of low power differential src clock pair with integrated 33 ohm rs. 28 srcc4_lrs out complement clock of low power differential src clock pair with 33 ohm integrated rs. 29 cpu_stop#/srcc5_lrs i/o stops all cpuclk, except those set to be free running clocks / com p lement clock of low p ower differential src p air with 33 ohm inte g rated rs. 30 pci_stop#/srct5_lrs i/o stops all pciclks at logic 0 level, when low. free running pciclks are not effected by this input. / true clock of low power differential src pair with inte g rated 33 ohm rs. 31 vddsrc pwr supply for src pll, 3.3v nominal 32 srcc6_lrs out complement clock of low power differential src clock pair with 33 ohm integrated rs. 33 srct6_lrs out true clock of low power differential src clock pair with integrated 33 ohm rs. 34 gndsrc pwr ground pin for the src outputs 35 srcc7_lrs/cr#_e i/o complement clock of differential push-pull src clock pair with 33 ohm integrated rs. / clock request control e for src6 pair. the power-up default is src7#, but this pin may also be used as a clock request control of src6 via smbus. before configuring this pin as a clock re quest pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high- z), the pin can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cre# enabled. 36 srct7_lrs/cr#_f i/o true clock of differential push-pull src clock pair/ clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring th is pin as a clock re q uest pin , the sr 37 vddsrcio pwr power supply for src outputs. 1.05v to 3.3v. 38 cpuc2_itp_lrs/srcc8_lrs out complement clock of low power differential cpu2/complement clock of differential src pair. 33 ohm rs is integrated. the functio n of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8# 1 = itp# 39 cput2_itp_lrs/srct8_lrs out true clock of low power differential cpu2/true clock of differential src pair. 33 ohm rs is integrated. the function of this p in is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 40 nc n/a no connect 41 vddcpuio pwr power supply for cpu outputs, 1.05v to 3.3v. 42 cpuc1_f_lrs out complementary clock of low power differential push-pull cpu output with integrated 33 ohm rs. this cpu clock i s free running during iamt. 43 cput1_f_lrs out true clock of differential push-pull cpu clock pair with integrated 33 ohm rs. this clock is free running dur ing iamt. 44 gndcpu pwr ground pin for the cpu outputs 45 cpuc0_lrs out complement clock of low power differential cpu clock pair with integrated 33 ohm rs. 46 cput0_lrs out true clock of low power differential cpu clock pair with integrated 33 ohm rs. 47 vddcpu pwr supply for cpu pll, 3.3v nominal 48 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 49 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_ mode is a real time in p ut to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 50 gndref pwr ground pin for the ref outputs. 51 x2 out crystal output, nominally 14.318mhz 52 x1 in crystal input, nominally 14.318mhz. 53 vddref pwr ref, xtal power supply, nominal 3.3v 54 ref0/fslc/test_sel i/o 14.318 mhz reference clock./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil _fs and vih_fs values. /test_sel: 3-level latched in p ut to enable test mode. refer to test clarification table 55 sdata i/o data pin for smbus circuitry, 5v tolerant. 56 sclk in clock pin of smbus circuitry, 5v tolerant.
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 4 56-pin ck505 for embedded systems ICS9EPRS525 is compliant intel ck505 yellow cover specification. this clock synthesizer provides a single chip solution for intel desktop chipsets. ICS9EPRS525 is driven with a 14.318mhz crystal. it also provides a tight ppm accuracy output for serial ata and pci-express support. general description block diagram power groups ref cpu(1:0) cpu pll1 ss osc ref src(7:3) pll2 non-ss pll3 ss 7 src8/itp pci(5:0) src2/sata src1/se(2:1) se outputs s ata dot96mhz pci33mhz src src s r c _ m a i n pci33mhz differential output src0/dot96 48mhz 48mhz cpu fsla ckpwrgd/pd# pci_stop# cpu_stop# cr#_(a:f) src5_en itp_en fslc/testsel fslb/testmode control logic x1 x2 vdd gnd 41, 47 44 16 15 12 11 911 53 50 28 pin number description master clock, analog cpuclk 26, 31, 37 23, 34 srcclk 20 19 usb 48 xtal, ref pciclk pll3/se dot 96mhz
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 5 56-pin ck505 for embedded systems absolute maximum ratings - dc parameters parameter symbol conditions min max units notes maximum supply voltage vddxxx supply voltage 4.6 v 7 maximum supply voltage vddxxx_io low-voltage differential i/o supply 3.8 v 7 maximum input voltage v ih 3.3v inputs 4.6 v 4,5,7 minimum input voltage v il any input gnd - 0.5 v 4,7 storage temperature ts - -65 150 c 4,7 input esd protection esd prot human body model 2000 v 6,7 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied, nor guaranteed. 3 maximum input voltage is not to exceed vdd electrical characteristics - input/supply/common output dc parameters parameter symbol conditions min max units notes ambient operating temp tambient - 0 70 c supply voltage vddxxx supply voltage 3.135 3.465 v suppl y volta g e vddxxx_io low-volta g e differential i/o suppl y 0.9975 3.465 v 10 input high voltage v ihse single-ended 3.3v inputs 2 v dd + 0.3 v 3 input low voltage v ilse single-ended 3.3v inputs v ss - 0.3 0.8 v 3 low threshold input- high voltage v ih_fs_tes t 3.3 v +/-5% 2 vdd + 0.3 v 8 low threshold input- fsc = '1' volta g e v ih_fs_fsc 3.3 v +/-5% 0.7 1.5 v 8 low threshold input- fsa,fsb = '1' voltage v ih_fs_fsab 3.3 v +/-5% 0.7 vdd+0.3 v low threshold input-low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v pci3/cfg0 input v il_cfghi optional input, 2.75v typ. 2.4 vdd+0.3 v 9, 10 pci3/cfg0 input v il_cfgmid optional input, 1.65v typ. 1.3 2 v 9, 10 pci3/cfg0 input v il_cfglo optional input, 0.55v typ. v ss - 0.3 0.9 v 9, 10 input leakage current i in v in = v dd , v in = gnd -5 5 ua 2 input leakage current i inres inputs with pull up or pull down resistors v in = v dd , v in = gnd -200 200 ua output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 i ddop3.3 full active, c l = full load; idd 3.3v 115 ma i ddopi o full active, c l = full load; idd io 55 ma 10 i ddiamt3.3 m1 mode, 3.3v rail 36 ma i ddiamtio m1 mode, io rail 10 ma i ddpd3.3 power down mode, 3.3v rail 5 ma i ddpdio power down mode, io rail 0.1 ma 10 input frequency f i v dd = 3.3 v 15 mhz pin inductance l p in 7nh c in logic inputs 1.5 5 pf c ou t output pin capacitance 6 pf c inx x1 & x2 pins 6 pf clk stabilization t stab from vdd power-up or de-assertion of pd to 1st clock 1.8 ms tdrive_cr_off t drcrof f output stop after cr deasserted 400 ns tdrive_cr_on t drcron output run after cr asserted 0 us tdrive_cpu t drsrc cpu output enable after pci_stop# de-assertion 10 ns tfall_se t fall 10 ns trise_se t rise 10 ns smbus voltage v dd 2.7 5.5 v low-level output voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to (min vih + 0.15) 1000 ns sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns maximum smbus operating frequency f smbus 100 khz spread spectrum modulation frequenc y f ssmod triangular modulation 30 33 khz input capacitance powerdown current fall/rise time of all 3.3v control inputs from 20-80% iamt mode current operating supply current
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 6 56-pin ck505 for embedded systems 1 signal is required to be monotonic in this region. 2 input leakage current does not include inputs with pull-up or pull-down resistors 4 intentionally blank 7 operation under these conditions is neither implied, nor guaranteed. 8 frequency select pins which have tri-level input 9 pci3/cfg0 is optional 10 if present. not all parts have this feature. 5 maximum vih is not to exceed vdd 6 human body model 3 3.3v referenced inputs are: pci_stop#, cpu_stop#, tme, src5_en, itp_en, sclkl, sdata, testmode, testsel, ckpwrgd and cr# inputs if s elec ted. notes on input/supply/common output dc parameters: (unless otherwise noted, guaranteed by design and characterization, not 100 % tested in production). clock jitter specs - low power differential outputs parameter symbol conditions min max units notes cpu jitter - cycle to cycle cpujc2c differential measurement 85 ps 1 src jitter - cycle to cycle srcjc2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotjc2c differential measurement 250 ps 1 1 jitter specs are specified as measured on a clock characterization board. system designers need to take special care not to us e these numbers, as the in-system performance will be somewhat degraded. the receiver emts (chispet or cpu) will have the receiver notes on dif output jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). ac electrical characteristics - low power differential outputs parameter symbol conditions min max units notes rising edge slew rate tslr averaging on 2.5 4 v/ns 2, 3 falling edge slew rate tflr averaging on 2.5 4 v/ns 2, 3 slew rate variation tslvar averaging on 20 % 1, 10 differential voltage swing vswing averaging off 300 mv 2 crossing point voltage vxabs averaging off 300 550 mv 1,4,5 crossing point variation vxabsvar averaging off 140 mv 1,4,9 maximum output voltage vhigh averaging off 1150 mv 1,7 minimum output voltage vlow averaging off -300 mv 1,8 duty cycle dcyc averaging on 45 55 % 2 cpu[1:0] skew cpuskew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpuskew20 differential measurement 150 ps 1 src[10:0] skew srcskew differential measurement 3000 ps 1,6 1 measurement taken for single ended waveform on a component test board (not in system) 2 measurement taken from differential waveform on a component test board. (not in system) 3 slew rate emastured through v_swing voltage range centered about differential zero 4 vcross is defined at the voltage where clock = clock#, measured on a component test board (not in system) 6 total distributed intentional src to src skew. maximum allowable interpair skew is 150 ps. 7 the max voltage including overshoot. 8 the min voltage including undershoot. 10 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window center ed on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage notes on dif output ac specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production ). 9 the total variation of all vcross measurements in any particular system. note this is a subset of v_cross min/mas (v_cross ab solute) allowed. the intent is to limit vcross induced modulation by setting c_cross_delta to be smaller than v_cross absolute 5 only applies to the differential rising edge (clock rising, clock# falling)
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 7 56-pin ck505 for embedded systems cpu src dot96 bmc133 100 100 100 100 ppm 85 125 250 125 ps -0.50% -0.50% 0 -0.50% % clock periods - differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 100.00 9.91400 9.99900 10.00000 10.00100 10.08600 ns 1,2 133.33 7.41425 7.49925 7.50000 7.50075 7.58575 ns 1,2 166.67 5.91440 5.99940 6.00000 6.00060 6.08560 ns 1,2 200.00 4.91450 4.99950 5.00000 5.00050 5.08550 ns 1,2 266.67 3.66462 3.74962 3.75000 3.75037 3.83537 ns 1,2 333.33 2.91470 2.99970 3.00000 3.00030 3.08530 ns 1,2 400.00 2.41475 2.49975 2.50000 2.50025 2.58525 ns 1,2 src/sata 100.00 9.87400 9.99900 10.00000 10.00100 10.12600 ns 1,2 dot96 96.00 10.16563 10.41563 10.41667 10.41771 10.66771 ns 1,2 clock periods - differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.91406 9.99906 10.02406 10.02506 10.02607 10.05107 10.13607 ns 1,2 133.00 7.41430 7.49930 7.51805 7.51880 7.51955 7.53830 7.62330 ns 1,2 166.25 5.91444 5.99944 6.01444 6.01504 6.01564 6.03064 6.11564 ns 1,2 199.50 4.91453 4.99953 5.01203 5.01253 5.01303 5.02553 5.11053 ns 1,2 266.00 3.66465 3.74965 3.75902 3.75940 3.75977 3.76915 3.85415 ns 1,2 332.50 2.91472 2.99972 3.00722 3.00752 3.00782 3.01532 3.10032 ns 1,2 399.00 2.41477 2.49977 2.50602 2.50627 2.50652 2.51277 2.59777 ns 1,2 src 99.75 9.87406 9.99906 10.02406 10.02506 10.02607 10.05107 10.17607 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. measurement window units ppm tolerance c y cle to c y cle jitter s p read ssc off center freq. mhz notes differential clock tolerances cpu 2 all lon g term accuracy specifications are g uaranteed with the assumption that the crystal input is tuned to exactly 14.31818mhz. measurement window units ssc on center freq. mhz notes cpu
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 8 56-pin ck505 for embedded systems intentional pci clock to clock delay 200 ps nominal steps pci0 pci1 pci2 pci3 pci4 pci_f5 1.0ns electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 33.33mhz output no spread 29.99700 30.00300 ns 2 33.33mhz output spread 30.08421 30.23459 ns 2 33.33mhz output no spread 29.49700 30.50300 ns 2 33.33mhz output nominal/spread 29.56617 30.58421 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 pin to pin skew t skew v t = 1.5 v 250 ps 2 intential pci to pci delay t skew v t = 1.5 v 100 200 ps 2 duty cycle d t1 v t = 1.5 v 45 55 % 2 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 2 t abs absolute min/max period output high current i oh output low current i ol clock period t period electrical characteristics - usb48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 2,4 clock period t p eriod 48.00mhz output nominal 20.83125 20.83542 ns 2,3 absolute min/max period t abs 48.00mhz output nominal 20.48125 21.18542 ns 2 clk high time t hi gh 8.216563 11.15198 v clk low time t low 7.816563 10.95198 v output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @min = 1.0 v -29 ma v oh @max = 3.135 v -23 ma v ol @ min = 1.95 v 29 ma v ol @ max = 0.4 v 27 ma rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 2 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 350 ps 2 output high current i oh output low current i ol
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 9 56-pin ck505 for embedded systems electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 2, 4 clock period tperiod 14.318mhz output nominal 69.82033 69.86224 ns 2, 3 absolute min/max period tabs 14.318mhz output nominal 69.83400 70.84800 ns 2 clk high time thigh 29.97543 38.46654 v clk low time tlow 29.57543 38.26654 v output high voltage voh ioh = -1 ma 2.4 v output low voltage vol iol = 1 ma 0.4 v output high current ioh voh @min = 1.0 v, voh@max = 3.135 v -33 -33 ma output low current iol vol @min = 1.95 v, vol @max = 0.4 v 30 38 ma rising edge slew rate tslr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate tflr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle dt1 vt = 1.5 v 45 55 % 2 jitter, cycle to cycle tjcyc-cyc vt = 1.5 v 1000 ps 2 1 edge rate in system is measured from 0.8v to 2.0v. 2 duty cycle, peroid and jitter are measured with respect to 1.5v 3 the average period over any 1us period of time 4 using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 mhz, 33.3333 33mhz and 48.000000mhz notes on se outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 10 56-pin ck505 for embedded systems fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz usb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 111 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. table 1: cpu frequency select table reserved 100.00 33.33 14.318 48.00 96.00 pin 17 pin 18 spread mhz mhz % 0000 0 0 0 1 100.00 100.00 0.5% down spread src clocks from src_main 0 0 1 0 100.00 100.00 0.5% down spread only srcclk1 from pll3 0 0 1 1 100.00 100.00 1% down spread only srcclk1 from pll3 0 1 0 0 100.00 100.00 1.5% down spread only srcclk1 from pll3 0 1 0 1 100.00 100.00 2% down spread only srcclk1 from pll3 0 1 1 0 100.00 100.00 2.5% down spread only srcclk1 from pll3 0111 n/a n/a n/a n/a 1 0 0 0 24.576 24.576 none 24.576mhz on se1 and se2 1 0 0 1 24.576 98.304 none 24.576mhz on se1, 98.304mhz on se2 1 0 1 0 98.304 98.304 none 98.304mhz on se1 and se2 1 0 1 1 27.000 27.000 none 27mhz on se1 and se2 1 1 0 0 25.000 25.000 none 25mhz on se1 and se2 1101 n/a n/a n/a n/a 1110 n/a n/a n/a n/a 1111 n/a n/a n/a n/a b1b1 b1b4 b1b3 b1b2 table 2: pll3 quick confi g uration ( onl y a pp lies in mode 0, see table 6 ) comment pll 3 disabled
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 11 56-pin ck505 for embedded systems table 3: io_vout select table b9b2 b9b1 b9b0 io_vou t 00 00.3v 00 10.4v 01 00.5v 01 10.6v 10 00.7v 10 10.8v 11 00.9v 11 11.0v table 4: device id table 000 0 b8b7 b8b6 b8b5 b8b4 comment 56 pin tssop table 5: slew rate selection table bit 1 bit 0 00 01 10 1 1 1x (2.0 v/ns) slew rate hi-z 0.7x (1.4v/ns) 0.8x (1.6 v/ns) table 6. pci3 configuration table pci3_cfg1 (b y te 11, bit 7) pci3_cfg0 (b y te 11, bit 6) low 0 or 1 0 0 0 0 = default mid 0 or 1 0 1 1 1 high tme=0 1 0 1 2 high tme=1 1 1 1 3 pci3/cfg0 hw strap pci2/tme hw strap confi g mode note: 2 bits are needed since cfg0 is tri-level input src_main_se l (b y te 0, bit 2) table 7. pll modes for pci3 configurations outputs ssc outputs ssc outputs ssc 0 = default cpu/src/ pci down usb na - - 100mhz pll1 (table 2 applies) 1 cpu down usb na src/pci down 100mhz pll3 2 cpu center usb na src/pci down 100mhz pll3 3 cpu center usb/lan25 na src/pci down 25mhz se pll2* *note: in mode 3, byte 8, bit (1:0) must be set to '1' to enable pin 17,18 config mode pll1 pll2 pll3 src1 pll source table 8. me clock selection table pcif5/ itp_en iamt_en cpu2_amt_en cpu1_amt_en x1 0 0 x1 0 1 11 1 0 11 1 1 cpu2 = iamt clock cpu1 and cpu2 both run in iamt mode reserved description default, cpu1 = iamt clock
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 12 56-pin ck505 for embedded systems pci_stop# power management smbus oe bit pci_stop# stoppable free running stoppable free running 1 running running running running ck= high ck# = low running ck= pull down ck# = low running disable x ck= pull down, ck# = low enable 0 low low single-ended clocks differential clocks (except cpu) lo w cpu_stop# power management smbus oe bi t pci_stop# sto pp able free runnin g 1 running running ck= high ck# = low running ck= pull down ck# = lo w running disable x enable 0 low differential clocks cr# power management smbus oe bi t cr# sto pp able free runnin g 1 running running 0 disable x enable ck= pull down, ck# = lo w ck = pull down, ck# = low differential clocks pd# power management device state w/o latched in p u t w/latched in p ut latches open power down m1 virtual power cycle to latches open cpu1 ck= pull down, ck# = low ck= pull down, ck# = low ck= pull down, ck# = low running differential clocks (except cpu1) ck= pull down ck# = low ck= pull down, ck# = low low hi-z single-ended clocks ck= pull down ck# = low ck= pull down ck# = low
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 13 56-pin ck505 for embedded systems general smbus serial interface information for the ICS9EPRS525 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the beginning byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controller (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 14 56-pin ck505 for embedded systems byte 0 fs readback and pll selection register bit pin name description type 0 1 default 7 - fslc cpu freq. sel. bit (most significant) r latch 6 - fslb cpu freq. sel. bit r latch 5 - fsla cpu freq. sel. bit (least si g nificant) r latch 4- iamt_en set via smbus or dynamically by ck505 if detects dynamic m1 rw legacy mode iamt enabled 0 3 reserved reserved rw 0 2 - src_main_sel select source for src main rw src main = pll1 src main = pll3 latch 1 - sata_sel select source for sata clock rw sata = src_main sata = pll2 0 0- pd_restore 1 = on power down de-assert return to last known state 0 = clear all smbus configurations as if cold power- on and go to latches open state this bit is ignored and treated at '1' if device is in iamt mode. rw configuration not saved configuration saved 1 byte 1 dot96 select and pll3 quick config register bit pin name description type 0 1 default 7 13/14 src0_sel select src0 or dot96 rw src0 dot96 0 6 - pll1_ssc_sel select 0.5% down or center ssc rw down spread center spread latch 5 pll3_ssc_sel select 0.5% down or center ssc rw down spread center spread 0 4 pll3_cf3 pll3 quick confi g bit 3 r w 0 3 pll3_cf2 pll3 quick config bit 2 rw 0 2 pll3_cf1 pll3 quick config bit 1 rw 0 1 pll3_cf0 pll3 quick confi g bit 0 r w 1 0 pci_sel pci_sel rw pci from pll1 pci from src_main 1 byte 2 output enable register bit pin name description type 0 1 default 7ref_oe output enable for ref, if disabled output is tri- stated rw output disabled output enabled 1 6 usb_oe output enable for usb rw output disabled output enabled 1 5 pcif5_oe output enable for pci5 rw output disabled output enabled 1 4 pci4_oe output enable for pci4 rw output disabled output enabled 1 3 pci3_oe output enable for pci3 rw output disabled output enabled 1 2 pci2_oe output enable for pci2 r w output disabled output enabled 1 1 pci1_oe output enable for pci1 rw output disabled output enabled 1 0 pci0_oe output enable for pci0 rw output disabled output enabled 1 byte 3 output enable register bit pin name description type 0 1 default 7 reserved reserved rw - - 1 6 reserved reserved rw - - 1 5 reserved reserved rw - - 1 4 src8/itp_oe output enable for src8 or itp rw output disabled output enabled 1 3 src7_oe output enable for src7 r w output disabled output enabled 1 2 src6_oe output enable for src6 rw output disabled output enabled 1 1 src5_oe output enable for src5 rw output disabled output enabled 1 0 src4_oe output enable for src4 rw output disabled output enabled 1 see table 1 : cpu frequency select table see table 2: pll3 quick configuration only applies if byte 0, bit 2 = 0.
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 15 56-pin ck505 for embedded systems byte 4 output enable and spread spectrum disable register bit pin name description type 0 1 default 7 src3_oe output enable for src3 rw output disabled output enabled 1 6 sata/src2_oe output enable for sata/src2 rw output disabled output enabled 1 5 src1_oe output enable for src1 r w output disabled output enabled 1 4 src0/dot96_oe output enable for src0/dot96 rw output disabled output enabled 1 3 cpu1_oe output enable for cpu1 rw output disabled output enabled 1 2 cpu0_oe output enable for cpu0 rw output disabled output enabled 1 1 pll1_ssc_on enable pll1's spread modulation rw spread disabled spread enabled 1 0 pll3_ssc_on enable pll3's spread modulation rw spread disabled spread enabled 1 byte 5 clock request enable/configuration register bit pin name description type 0 1 default 7 cr#_a_en enable cr#_a (clk req), pci0_oe must be = 1 for this bit to take effect rw disable cr#_a enable cr#_a 0 6 cr#_a_sel sets cr#_a to control either src0 or src2 rw cr#_a -> src0 cr#_a -> src2 0 5 cr#_b_en enable cr#_b (clk req) rw disable cr#_b enable cr#_b 0 4 cr#_b_sel sets cr#_b -> src1 or src4 rw cr#_b -> src1 cr#_b -> src4 0 3 cr#_c_en enable cr#_c (clk req) rw disable cr#_c enable cr#_c 0 2 cr#_c_sel sets cr#_c -> src0 or src2 r w cr#_c -> src0 cr#_c -> src2 0 1 cr#_d_en enable cr#_d (clk req) rw disable cr#_d enable cr#_d 0 0 cr#_d_sel sets cr#_d -> src1 or src4 rw cr#_d -> src1 cr#_d -> src4 0 byte 6 clock request enable/configuration and stop control register bit pin name description type 0 1 default 7 cr#_e_en enable cr#_e (clk req) -> src6 rw disable cr#_e enable cr#_e 0 6 cr#_f_en enable cr#_f (clk req) -> src8 r w disable cr#_f enable cr#_f 0 5 reserved reserved rw - - 0 4 reserved reserved rw - - 0 3 reserved reserved r w --0 2 reserved reserved rw - - 0 1 sscd_stp_crtl (src1) if set, sscd (src1) stops with pci_stop# rw free running stops with pci_stop# assertion 0 0 src_stp_crtl if set, srcs (except src1) stop with pci_stop# rw free running stops with pci_stop# assertion 0 byte 7 vendor id/ revision id bit pin name description type 0 1 default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 vendor id ics is 0001, binary revision id vendor specific
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 16 56-pin ck505 for embedded systems byte 8 device id and output enable register bit pin name description type 0 1 default 7device_id3 r 0 6device_id2 r 0 5device_id1 r 0 4device_id0 r 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 se1_oe output enable for se1 rw disabled enabled 0 0 se2_oe output enable for se2 rw disabled enabled 0 byte 9 output control register bit pin name description type 0 1 default 7pcif5 stop en allows control of pcif5 with assertion of pci_stop# rw free running stops with pci_stop# assertion 0 6 tme_readback truested mode enable (tme) strap status r normal operation no overclocking latch 5 ref strength sets the ref output drive strength rw 1x (2loads) 2x (3 loads) 1 4 test mode select allows test select, ignores ref/fsc/testsel rw outputs hi-z outputs = ref/n 0 3 test mode entry allows entry into test mode, ignores fsb/testmode rw normal operation test mode 0 2 io_vout2 io output voltage select (most significant bit) rw 1 1 io_vout1 io output voltage select rw 0 0 io_vout0 io output voltage select (least significant bit) rw 1 byte 10 stop enable register bit pin name description type 0 1 default 7 src5_en readback readback of src5 enable latch r cpu/pci stop enabled src5 enabled latch 6 reserved rw - - 0 5 reserved rw - - 0 4 reserved rw - - 0 3 reserved rw - - 0 2 reserved rw - - 0 1 cpu 1 stop enable enables control of cpu1 with cpu_stop# rw free running stoppable 1 0 cpu 0 stop enable enables control of cpu 0 with cpu_stop# rw free running stoppable 1 byte 11 iamt enable register bit pin name description type 0 1 default 7 pci3_cfg1 r latch 6 pci3_cfg0 r latch 5 reserved reserved r w --0 4 reserved reserved rw - - 1 3 cpu2_amt_en determines if cpu2 runs in m1 mode. only valid if itp_en=1. see note. rw does not run runs 0 2 cpu1_amt_en determines if cpu1 runs in m1 mode. see note. rw does not run runs 1 1 pci-e_gen2 determines if pci-e gen2 compliant r non-gen2 pci-e gen2 compliant 1 0 cpu 2 stop enable enables control of cpu 0 with cpu_stop# rw free running stoppable 1 note: a value of '00' for bit(3:2) in byte 11 is reserved and not a valid configuration. reserved table of device identifier codes, used for differentiating between ck505 package options, etc. 56-pin device see table 3: v_io selection (default is 0.8v) see pci3 configuration table 28 see pci3 configuration table
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 17 56-pin ck505 for embedded systems byte 12 byte count register bit pin name description type 0 1 default 7 reserved rw 0 6 reserved rw 0 5bc5 rw 0 4bc4 rw 0 3bc3 rw 1 2bc2 rw 1 1bc1 rw 0 0bc0 rw 1 byte 13 to 28 reserved byte 29 slew rate control bit pin name description rw 0 1 default 7 usb_slew1 usb slew rate control (msb) rw 1 6 usb_slew0 usb slew rate control (lsb) rw 0 5 pci_slew1 pci slew rate control (msb) rw 1 4 pci_slew0 pci slew rate control (lsb) rw 1 3 reserved rw 1 2 ref slew rate changes ref slew rate rw 1.2v/ns 2.2v/ns 1 1 reserved rw 0 0 reserved rw 0 read back byte count register, max bytes = 32 see slew rate selection table see slew rate selection table
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 18 56-pin ck505 for embedded systems test clarification table comments fslc/ test_sel hw pin fslb/ test_mode hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n h w s w power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode fslc./test_sel -->3-level latched input if power-up w/ v>2.0v then use test_sel if power-up w/ v<2.0v then use fslc fslb/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 during power-up, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control b9b3: 1= enter test mode, default = 0 (normal operation) b9b4: 1= ref/n, default = 0 (hi-z)
idt tm 56-pin ck505 for embedded intel systems 1614b?01/21/10 ICS9EPRS525 19 56-pin ck505 for embedded systems index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 56 13.90 14.10 .547 .555 10-0039 56-lead 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) ref er ence do c.: jedec pub licat io n 9 5, m o-153 ordering information part/order number shipping packaging package temperature 9eprs525aglf tubes 56-pin tssop 0 to +70 c 9eprs525aglft tape and reel 56-pin tssop 0 to +70 c 9eprs525agilf tubes 56-pin tssop -40 to +85 c 9eprs525agilft tape and reel 56-pin tssop -40 to +85 c parts that are ordered w ith a ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. due to package size constraints, actual top-side marking may differ from the full orderable part number.
ICS9EPRS525 56-pin ck505 for embedded systems 20 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm this product is protected by united states patent no. 7,342,420 and other patents. revision history rev. issue date description page # 0.1 7/31/2009 initial release - a 8/19/2009 released to final. b 1/21/2010 updated power groups table. 4

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